Exynos542x: add L2 control register configuration

Exynos542x: add L2 control register configuration

This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
   0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
   We need to restore this here due to switching.

Signed-off-by: Abhilash Kesavan <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>